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PRELIMINARY
W211B
FTG for 440BX, VIA Apollo Pro-133, and ProMedia
Features
* Maximized EMI Suppression using Cypress's Spread Spectrum technology * Single-chip system frequency synthesizer for 440BX, VIA Apollo Pro-133, and ProMedia * Supports Intel(R) Pentium(R) II and Cyrix class processors * Two copies of CPU output * Six copies of PCI output * One 48-MHz output for USB * One 24-MHz or 48-MHz output for SIO * Two buffered reference outputs * One IOAPIC output * Thirteen SDRAM outputs provide support for 3 DIMMs * Supports frequencies up to 200 MHz * SMBus interface for programming * Power management control inputs * Available in 48-pin SSOP * SDRAM Range = 66 MHz to 133 MHz SDRAMIN to SDRAM0:12 Delay:........................4.5 - 6.0 ns Table 1. Mode Input Table Mode Pin 2 0 CPU_STOP# 1 REF0 Table 2. Pin Selectable Frequency Input Address CPU_F, PCI_F, Spread FS3 FS2 FS1 FS0 CPU1 (MHz) 1:5 (MHz) Spectrum 1 1 1 1 133.3 33.3 0.5% 1 1 1 0 75 37.5 OFF 1 1 0 1 100.2 33.3 0.5% 1 1 0 0 66.8 33.4 0.5% 1 0 1 1 79 39.5 OFF 1 0 1 0 110 36.7 OFF 1 0 0 1 115 38.3 OFF 1 0 0 0 120 30 OFF 0 1 1 1 133.3 33.3 -0.5% 0 1 1 0 83 27.7 OFF 0 1 0 1 100.2 33.3 -0.5% 0 1 0 0 66.8 33.4 -0.5% 0 0 1 1 122 30.5 -0.5% 0 0 1 0 129 32.3 OFF 0 0 0 1 138 34.5 OFF 0 0 0 0 95 31.7 -0.5%
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps CPU to CPU Output Skew: ......................................... 175 ps PCI to PCI Output Skew: ............................................ 500 ps VDDQ3: .................................................................... 3.3V5% VDDQ2: .................................................................... 2.5V5%
Block Diagram
X1 X2 XTAL OSC
VDDQ3 REF0/(CPU_STOP#) REF1/FS0
Pin Configuration[1]
VDDQ3 REF0/(CPU_STOP#) GND X1 X2 VDDQ3 PCI0/MODE PCI1/FS1* GND PCI2 PCI3 PCI4 PCI5 VDDQ3 SDRAMIN GND SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SMBus SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ2 IOAPIC REF1/FS0* GND CPU_F CPU1 VDDQ2 PWRDWN# SDRAM12 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VDDQ3 48MHz/FS2* 24_48MHz/FS3^
PLL Ref Freq
I/O Pin Control
PWRDWN#
CPU_F Stop Clock Control
/2,3,4
W211B
CPU1
PLL 1
VDDQ3 PCI0/MODE PCI1/FS1 PCI2 PCI3 PCI4 PCI5 VDDQ3 48MHz/FS2
/2
SDATA SCLK
SMBus Logic PLL2
{
SDRAMIN
13
24_48MHz/FS3 VDDQ3 SDRAM0:12
Note: 1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input FS3 has an internal pull-down resistor.
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation Document #: 38-07174 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised September 25, 2001
PRELIMINARY
Pin Definitions
Pin Name CPU_F CPU1 PCI2:5 Pin No. 44 43 10, 11, 12, 13 Pin Type O O O Pin Description
W211B
Free-running CPU Clock: Output voltage swing is controlled by the voltage applied to VDDQ2. See Table 2 and Table 6 for detailed frequency information. CPU Clock Output 1: This CPU clock output is controlled by the CPU_STOP# and PWRDWN# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the PWRDWN# control pin. Frequency is set by FS0:3 inputs or through serial input interface, see Tables 2 and 6 for details. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed PCI Clock Output/Frequency Select 1: As an output, frequency is set by FS0:3 inputs or through serial input interface. This output is controlled by the PWRDWN# input. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Fixed PCI Clock Output/Mode: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Table 2 and Table 6. This output is controlled by the PWRDWN# input. This pin also serves as a power-on strap option to determine the function of pin 2, see Table 1 for details. PWRDWN# input: LVTTL-compatible input that places the device in power-down mode when held LOW. IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. This output is disabled when PWRDWN# is set LOW. 48-MHz Output/Frequency Select 2: 48 MHz is provided in normal operation. In standard PC systems, this output can be used as the reference for the Universal Serial Bus host controller. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. 24_48-MHz Output/Frequency Select 3: In standard PC systems, this output can be used as the clock input for a Super I/O chip. The output frequency is controlled by Configuration Byte 3 bit[6]. The default output frequency is 48 MHz. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Reference Clock Output 1/Frequency Select 2: 3.3V 14.318-MHz output clock. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Upon power-up, FS0 input will be latched which will set clock frequencies as described in Table 2. Reference Clock Output 0 or CPU_STOP# Input Pin: Function is determined by the MODE pin. When CPU_STOP# input is asserted LOW, it will disable CPU1 output and drive it to logic 0. When this pin is configured as an output, this pin becomes a 3.3V 14.318-MHz output clock. Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs (SDRAM0:12). Buffered Outputs: These thirteen dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when PWRDWN# input is set LOW. Clock pin for SMBus circuitry. Data pin for SMBus circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output, connect to 3.3V supply. Power Connection: Power supply for IOAPIC, CPU_F, and CPU1 output buffers, connect to 2.5V or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane. Page 2 of 16
PCI1/FS1
8
I/O
PCI0/MODE
7
I/O
PWRDWN# IOAPIC 48MHz/FS2
41 47 26
I O I/O
24_48MHz/ FS3
25
I/O
REF1/FS0
46
I/O
REF0/ CPU_STOP#
2
I/O
SDRAMIN SDRAM0:12
15
38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17, 40
I O
SCLK SDATA X1
24 23 4
I I/O I
X2 VDDQ3 VDDQ2 GND
5 1, 6, 14, 19, 27, 30, 36 42, 48
3, 9, 16, 22, 33, 39, 45
I P P G
Document #: 38-07174 Rev. **
PRELIMINARY
Overview
The W211B was developed as a single-chip device to meet the clocking needs of both Intel 440BX and VIA Apollo Pro-133 core logic chip sets. In addition to the typical outputs provided by a standard FTG, the W211B adds a thirteenth output buffer, supporting SDRAM DIMM modules in conjunction with the chipset. Cypress's proprietary spread spectrum frequency synthesis technique is a feature of the CPU and PCI outputs. When enabled, this feature reduces the peak EMI measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them.
W211B
Upon W211B power-up, the first 2 ms of operation is used for input logic selection. During this period, the five I/O pins (7, 8, 25, 26, 46) are three-stated, allowing the output strapping resistor on the l/O pins to pull the pins and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic "0" or "1" condition of the l/O pin is latched. Next the output buffer is enabled, converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock outputs is <40 (nominal), which is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, the specified output frequency is delivered on the pin, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
Functional Description
I/O Pin Operation Pins 7, 8, 25, 26, and 46 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after powerup, the logic state of each pin is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to "0," connection to VDD sets a latch to "1." Figure 1 and Figure 2 show two suggested methods for strapping resistor connections.
VDD Output Strapping Resistor 10 k (Load Option 1) W211B Output Buffer Power-on Reset Timer Output Three-state Control Logic 10 k (Load Option 0)
D
Series Termination Resistor R Clock Load
Q
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
VDD 10 k W211B Output Buffer Power-on Reset Timer Output Three-state Control Logic R
Output Strapping Resistor Series Termination Resistor Clock Load
Resistor Value R
Q
D
Data Latch
Figure 2. Input Logic Selection Through Jumper Option Document #: 38-07174 Rev. ** Page 3 of 16
PRELIMINARY
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. As shown in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F)
W211B
Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is specified in Table 6. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1-0 in data byte 0 of the SMBus data stream. Refer to Table 6 for more details.
EMI Reduction
SSFTG
Typical Clock
Amplitude (dB)
Amplitude (dB)
Spread Spectrum Enabled
NonSpread Spectrum
Frequency Span (MHz) Center Spread
Frequency Span (MHz) Down Spread
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX FO
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN FO
Figure 4. Typical Modulation Profile
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100%
PRELIMINARY
Serial Data Interface
The W211B features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W211B initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the Table 3. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description Common Application
W211B
chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 3 summarizes the control functions of the serial data interface. Operation Data is written to the W211B in eleven bytes of eight bits each. Bytes are written in the order shown in Table 4.
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused PCI slots. Provides CPU/PCI frequency selections through software. Frequency is changed in a smooth and controlled fashion. Enables or disables spread spectrum clocking. Puts clock output into a high impedance state. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. For EMI reduction. Production PCB testing.
CPU Clock Frequency Selection
Spread Spectrum Enabling Output Three-state (Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0.
Table 4. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W211B to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W211B is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W211B, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W211B, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in Data Bytes 0-7 set internal W211B registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 5, Data Byte Serial Configuration Map.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10 11
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7
Refer to Table 5
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PRELIMINARY
Writing Data Bytes Each bit in Data Bytes 0-7 controls a particular device function except for the "reserved" bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit Table 5. Data Bytes 0-7 Serial Configuration Map Affected Pin Bit(s) 7 6 5 4 3 2 1 0 Data Byte 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Byte 3 7 6 5 4 3 2 1 --26 25 -21, 20, 18, 17 32, 31, 29, 28 -SEL_48MHz 48MHz 24_48MHz -SDRAM8:11 SDRAM4:7 (Reserved) SEL 48MHz as the output frequency for 24_48MHz Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable -24 MHz Low Low -Low Low -48 MHz Active Active -Active Active ----40 -43 44 -7 -13 12 11 10 8 ----SDRAM_12 -CPU1 CPU_F -PCI0 -PCI5 PCI4 PCI3 PCI2 PCI1 (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable ----Low -Low Low -Low -Low Low Low Low Low ----Active -Active Active -Active -Active Active Active Active Active Pin No. --------Pin Name --------Control Function (Reserved) SEL_2 SEL_1 SEL_0 Hardware/Software Frequency Select SEL_4 SEL_3 Normal 0 -See Table 6 See Table 6 See Table 6 Hardware Software See Table 6 See Table 6 Three-stated Data Byte 0 -Bit Control 1
W211B
7. Table 5 gives the bit formats for registers located in Data Bytes 0-7. Table 6 details additional frequency selections that are available through the serial data interface.
Default 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 1
Data Byte 2
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PRELIMINARY
Table 5. Data Bytes 0-7 Serial Configuration Map (continued) Affected Pin Bit(s) 0 Pin No. 38, 37, 35, 34 -----------47 --46 2 ----------------Pin Name SDRAM0:3 Control Function Clock Output Disable 0 Low Bit Control 1 Active
W211B
Default 1
Data Byte 4 7 6 5 4 3 2 1 0 Data Byte 5 7 6 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 0 Data Byte 7 7 6 5 4 3 2 1 0 --------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ----------------0 0 0 0 0 0 0 0 --------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ----------------0 0 0 0 0 0 0 0 ---IOAPIC --REF1 REF0 (Reserved) (Reserved) (Reserved) Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable ---Low --Low Low ---Active --Active Active 0 0 0 1 0 0 1 1 --------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ----------------0 0 0 0 0 0 0 0
Document #: 38-07174 Rev. **
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PRELIMINARY
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 0, Bit 3 = 1 Bit 2 SEL_4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 1 SEL_3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Bit 6 SEL_2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Bit 5 SEL_1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Bit 4 SEL_0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU 133.3 75 100.2 66.8 79 110 115 120 133.3 83 100.2 66.8 122 129 138 95 85 87.5 90 92.5 95 147 152 154 157 159 162 166 171 180 190 200 PCI 33.3 37.5 33.3 33.4 39.5 36.7 38.3 30 33.3 27.7 33.3 33.4 30.5 32.3 34.5 31.7 28.3 29.2 30 30.8 31.7 36.8 30.4 30.8 31.4 31.8 32.4 33.2 34.2 36 38 40 Output Frequency
W211B
Spread Spectrum 0.5% OFF 0.5% 0.5% OFF OFF OFF OFF -0.5% OFF -0.5% -0.5% -0.5% OFF OFF -0.5% OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
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PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
W211B
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min.) Unit V C C C kV
Parameter VDD, VIN TSTG TB TA ESDPROT
Description Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Input ESD Protection
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5%
Parameter Supply Current IDD IDD Logic Inputs VIL VIH IIL IIH VOL VOH VOH IOL Input Low Voltage Input High Voltage Input Low Current[3] Input High Current[3] Output Low Voltage Output High Voltage Output High Voltage Output Low Current CPU_F:1, IOAPIC CPU_F, CPU1 PCI0:5 IOAPIC REF0:1 48-MHz SDRAM0:15,_F 24-MHz IOH Output High Current CPU_F, CPU1 PCI0:5 IOAPIC REF0:1 48-MHz 24-MHz SDRAM0:15,_F IOL = 1 mA IOH = -1 mA IOH = -1 mA VOL = 1.25V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.5V VOH = 1.5V VOL = 1.5V VOH = 1.25V VOH = 1.5V VOH = 1.25V VOH = 1.5V VOH = 1.5V VOH = 1.5V VOL = 1.5V 3.1 2.2 27 20.5 40 25 25 75 25 25 31 40 27 27 25 95 57 53 85 37 37 95 37 55 55 87 44 44 37 110 97 139 140 76 76 120 76 97 139 155 94 94 76 130 GND - 0.3 2.0 0.8 VDD + 0.3 -25 10 50 V V A A mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA 3.3V Supply Current 2.5V Supply Current CPU_F; CPU1=100 MHz Outputs Loaded[2] CPU_F; CPU1=100 MHz Outputs Loaded[2] 260 25 mA mA Description Test Condition Min. Typ. Max. Unit
Clock Outputs
Notes: 2. All clock outputs loaded with 6 60 transmission lines with 22-pF capacitors. 3. W211B logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.
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PRELIMINARY
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5% (continued)
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input Threshold Voltage[4] Load Capacitance, Imposed on External Crystal[5] X1 Input Capacitance[6] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 VDDQ3 = 3.3V 1.65 14 28 5 6 7 Description Test Condition Min. Typ. Max.
W211B
Unit V pF pF pF pF nH
Pin Capacitance/Inductance
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%,VDDQ2 = 2.5V 5% fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum is disabled. CPU Clock Outputs, CPU_F, 1 (Lump Capacitance Test Load = 20 pF) Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Rise Edge Rate Test Condition/ Comments Measured on rising edge at 1.25 Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 0.4V to 2.0V CPU = 66.6 MHz 15 5.2 5.0 1 1 45 4 4 55 200 15.5 CPU = 100 MHz 10 3.0 2.8 1 1 45 4 4 55 200 10.5 CPU = 133 MHz 7.5 1.87 1.67 1 1 45 4 4 55 250 8.0 ns ns ns V/ns V/ns % ps Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Output Fall Edge Measured from 2.0V to Rate 0.4V Duty Cycle Jitter, Cycle-to-Cycle Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value.
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
175 3
ps ms
Zo
20
20
20
Notes: 4. X1 input threshold voltage (typical) is VDDQ3/2. 5. The W211B contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
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PRELIMINARY
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF Parameter tP tH tL tR tF tD tJC tSK tO fST Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 30 1.5 Min. 30 12 12 1 1 45 Typ.
W211B
Max.
Unit ns ns ns
4 4 55 250 500 4 3
V/ns V/ns % ps ps ns ms
Zo
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 1 1 45 Min. Typ. 14.318 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
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PRELIMINARY
SDRAM 0:12 Clock Outputs (Lump Capacitance Test Load = 22 pF) SDRAMIN = 66.8 MHz Parameter tP tH tL tR tF tD tSK tPD Zo Description Period High Time Low Time Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V 15 5.2 5.0 1 1 45 4 4 55 250 4.5 15 6.0 4.5 15 15.5 SDRAMIN = 100 MHz 10 3.0 2.0 1 1 45 4 4 55 250 6.0 4.5 15 10.5
W211B
SDRAMIN = 133 MHz 7.5 1.87 1.67 1 1 45 4 4 55 250 6.0 8.0 ns ns ns V/ns V/ns % ps ns
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Output Rise Edge Measured from 0.4V to 2.4V Rate Output Fall Edge Measured from 2.4V to 0.4V Rate Duty Cycle Output Skew Propagation Delay AC Output Impedance Measured on rising and falling edge at 1.5V Measured on rising and falling edge at 1.5V Measured from SDRAMIN Average value during switching transition. Used for determining series termination value.
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
Document #: 38-07174 Rev. **
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PRELIMINARY
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 24 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (24.004 - 24)/24 (14.31818 MHz x 57/34 = 24.004 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 24.004 +167 57/34
W211B
Max.
Unit MHz ppm
2 2 55 3
V/ns V/ns % ms
Zo
Ordering Information
Ordering Code W211B Package Name H Package Type 48-pin SSOP (300 mils)
Document #: 38-07174 Rev. **
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PRELIMINARY
Layout Example
+3.3V Supply FB
VDDQ3
.005mF 10mF
W211B
+2.5V Supply FB
VDDQ2
C4
C3
C1
10mF
.005mf
C2
G G
G
G
G G
G
G
G
1V 2G 3G 4 5G 6V 7G 8 9G 10 11 12 13 G 14 V 15 G 16 G 17 18 G 19 V 20 G 21 22 G 23 24 G
48 G 47 46 G 45 44 G 43 V 42 G 41 40 G 39 38 G 37 V 36 G 35 34 G 33 32 G 31 V 30 G 29 28 V 27 26 G 25
V
G
G
FB = Vishay ILB1206 - 300 (300 @ 100 MHz) or TDK ACB2012L-120 Cermaic Caps C1 & C3 = 10 - 22 F C2 & C4 = .005 F C5 = 10 F G = VIA to GND plane layer C6 = .1 F
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors *Note: When using the 48 MHz for clocking video circuitry, then a 10 + 10 F ceramic filter should be used on pin 27.
W211B
G
G
G
*
Document #: 38-07174 Rev. **
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PRELIMINARY
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
W211B
Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102
Document #: 38-07174 Rev. **
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(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
Document Title: W211B FTG for 440BX, VIA Apollo Pro-133, and ProMedia Document Number: 38-07174 REV. ** ECN NO. 110284 Issue Date 11/05/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00849 to 38-07174
W211B
Document #: 38-07174 Rev. **
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